In storage and communication systems, a read signal (e.g., read back from storage media) or a received signal (e.g., received via a communications channel) is transformed from an analog signal to a digital signal. In order for downstream digital processors in a receiver or a read processor to operate properly, the timing parameters (e.g., frequency and phase) of an analog to digital converter must match that of desired timing parameters. For example, if a random sampling phase is used, at some phases the signal folds back constructively (i.e., increases signal power) whereas at other phases the signal folds back destructively (i.e., decreases signal power) and performance is degraded in the latter case.
Some systems use a closed loop system where there is a feedback path which adjusts the timing parameters of the analog to digital converter. This is often done using a known data portion of a sector or packet, for example a preamble portion and/or synchronization mark portion where the content is known ahead of time. It would be desirable if new techniques could be developed, for example that use simpler processing (which corresponds to a smaller die size and less cost) and/or improve the performance or efficiency of the system.